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DG884
Vishay Siliconix
8 x 4 Wideband Video Crosspoint Array
FEATURES
Routes Any Input to Any Output Wide Bandwidth: 300 MHz Low Crosstalk: -85 dB @ 5 MHz Double Buffered TTL-Compatible Latches with Readback D Low rDS(on): 45 W D Optional Negative Supply D D D D
BENEFITS
D D D D D D D Reduced Board Space Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing Allows Bipolar Signal Swings Reduced Insertion Loss High Reliability
APPLICATIONS
D Wideband Signal Routing and Multiplexing D High-End Video Systems D NTSC, PAL, SECAM Switchers D Digital Video Routing D ATE Systems
DESCRIPTION
The DG884 contains a matrix of 32 T-switches configured in an 8 4 crosspoint array. Any of the IN/OUT pins may be used as an input or output. Any of the IN pins may be switched to any or simultaneously to all OUT pins. Control data is loaded individually into four Next Event latches. When all Next Event latches have been programmed, data is transferred into the Current Event latches via a SALVO command. Current Event latch data readback is available to poll array status. Output disable capabilities make it possible to parallel multiple DG884s to form larger switch arrays. DIS outputs provide control signals used to place external buffers in a power saving mode. For additional information see applications note AN504 (FaxBack document number 70610).
The DG884 is built on a proprietary D/CMOS process that combines low capacitance switching DMOS FETs with low power CMOS control logic and drivers. The ground lines between adjacent signal input pins help to reduce crosstalk. The low on-resistance and low on-capacitance of the DG884 make it ideal for video and wideband signal routing.
FUNCTIONAL BLOCK DIAGRAM
IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8
OUT1 OUT2 8 4 Switch Matrix OUT3 OUT4
Decode Logic, Switch Drivers
4 Disable Outputs
WR CS B1 B0 I/O Control Logic
Current Event Latches
RS SALVO
Next Event Latches
I/O A3 Document Number: 70071 S-52433--Rev. G, 20-Dec-04
A2 A1
A0 www.vishay.com
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DG884
Vishay Siliconix
PIN CONFIGURATION AND ORDERING INFORMATION
OUT1 GND
OUT2 GND
OUT3 GND
6
5
4
3
2
1 44 43 42 41 40
IN2 GND IN3 GND IN4 GND IN5 GND IN6 GND IN7
OUT4
GND
GND
GND
IN 1
7 8 9 10 11 12 13 14 15 16 17 PLCC and CLCC Top View
39 38 37 36 35 34 33 32 31 30 29
DGND VL RS SALVO WR A3 A2 A1 A0 CS I/O
ORDERING INFORMATION
Temp Range
-40 to 85_C -55 to 125_C
Package
44-Pin PLCC 44-Pin CLCC
Part Number
DG884DN DG884AM/883
18 19 20 21 22 23 24 25 26 27 28 GND IN8 GND V- DIS 1 DIS 2 DIS 3 DIS 4 B0 V+ B1
TRUTH TABLE I
RS
1 1 1 1 1 1 1 1 1 1 0
I/O
0 0 0 0 0 0 0 0 1 1 X
CS
1 0 0 0 X 0 X 0 1 0 X
WR
SALVO
1 1 No change to Next Event latches
Actions
Next Event latches loaded as defined in table below Next Event latches are transparent. Next Event data latched-in Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all new crosspoint addresses change simultaneously when SALVO goes low.
0
1 1
1 X 1 0 1 1 1 0 1 1 1 0
Current Event latches are transparent Current Event data latched-in Both next and Current Event latches are transparent A0, A1, A2, A3 - High impedance A0, A1, A2, A3 become outputs and reflect the contents of the Current Event latches. B0, B1 determine which Current Event latches are being read All crosspoints opened (but data in Next Event latches is preserved)
All other states are not recommended.
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Document Number: 70071 S-52433--Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TRUTH TABLE II
WR B1 B0 A3 A2
0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X
A1
0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X
A0
0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X
Next Event Latches
IN1 to OUT1 Loaded IN2 to OUT1 Loaded IN3 to OUT1 Loaded IN4 to OUT1 Loaded IN5 to OUT1 Loaded IN6 to OUT1 Loaded IN7 to OUT1 Loaded IN8 to OUT1 Loaded Turn Off OUT1 Loaded IN1 to OUT2 Loaded IN2 to OUT2 Loaded IN3 to OUT2 Loaded IN4 to OUT2 Loaded IN5 to OUT2 Loaded IN6 to OUT2 Loaded IN7 to OUT2 Loaded IN8 to OUT2 Loaded Turn Off OUT2 Loaded IN1 to OUT3 Loaded IN2 to OUT3 Loaded IN3 to OUT3 Loaded IN4 to OUT3 Loaded IN5 to OUT3 Loaded IN6 to OUT3 Loaded IN7 to OUT3 Loaded IN8 to OUT3 Loaded Turn Off OUT3 Loaded IN1 to OUT4 Loaded IN2 to OUT4 Loaded IN3 to OUT4 Loaded IN4 to OUT4 Loaded IN5 to OUT4 Loaded IN6 to OUT4 Loaded IN7 to OUT4 Loaded IN8 to OUT4 Loaded Turn Off OUT4 Loaded
0
0
1
0
0
1
1
0 0
1
0
1
0
1
1
1
0 Note:
When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN1 to OUT1 thru OUT4 requires A0, A1, A2 = 0 to be latched with each combination of B0, B1. When RS = 0, all four DIS outputs pull low simultaneously.
ABSOLUTE MAXIMUM RATINGS
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 21 V V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 21 V V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -10 V to 0.3 V VL to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to (V+) + 0.3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) - 0.3 V to (VL) + 0.3 V or 20 mA, whichever occurs first VS, VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) - 0.3 V to (V-) + 14 V or 20 mA, whichever occurs first CURRENT (any terminal) Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA CURRENT (S or D) Pulsed 1 ms 10% duty . . . . . . . . . . . . . . . . . . . . . . 40 mA Storage Temperature (A Suffix) . . . . . . . . . . . . . . . . . . . . -65 to 150_C (D Suffix) . . . . . . . . . . . . . . . . . . . . -65 to 125_C Operating Temperature (A Suffix) . . . . . . . . . . . . . . . . . . . . -55 to 125_C (D Suffix) . . . . . . . . . . . . . . . . . . . . . -40 to 85_C
Power Dissipation (Package)a 44-Pin Quad J Lead PLCCb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 mW 44-Pin Quad J Lead Hermetic CLCCc . . . . . . . . . . . . . . . . . . . . . . . . 1200 mW
Notes: a. All leads soldered or welded to PC board. b. Derate 6 mW/_C above 75_C. c. Derate 16 mW/_C above 75_C.
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Specified
V+ = 15 V, V- = -3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Parameter Analog Switch
Analog Signal Rangee Drain-Source On-Resistance Resistance Match Between Channels Source Off Leakage Current Drain Off Leakage Current Total Switch On Leakage Current
Symbol
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
VANALOG rDS(on) DrDS(on) IS(off) ID(off) ID(on)
V- = -5 V IS = -10 mA, VD = 0 V VAIH = 2 0 V VAIL = 0 8 V 2.0 V, 0.8 Sequence Each Switch On VS = 8 V, VD = 0 V, RS = 0.8 V VS = 0 V, VD = 8 V, RS = 0.8 V VS = VD = 8 V
Full Room Full Room Room Full Room Full Room Full 45 3
-5
8 90 120 9
-5
8 90 120 9
V
W
-20 -200 -20 -200 -20 -2000
20 200 20 200 20 2000
-20 -200 -20 -200 -20 -200
20 200 20 200 20 200 nA
Digital Input/Output
Input Voltage High Input Voltage Low Address Input Current Address Output Current DIS Pin Sink Current VAIH VAIL IAI IAO IDIS VAI = 0 V or 2 V or 5 V VAO = 2.7 V, See Truth Table VAO = 0.4 V, See Truth Table Full Full Room Full Room Room Room 0.1 -600 1500 1.5 500 -1 -10 2 0.8 1 10 -200 500 mA -1 -10 2 0.8 1 10 -200 mA V
Dynamic Characteristics
On State Input Capacitancee Off State Input Capacitancee Off State Output Capacitancee Transition Time Break-Before-Make Interval SALVO, WR Turn On Time SALVO, WR Turn Off Time Charge Injection Matrix Disabled Crosstalk Adjacent Input Crosstalk All Hostile Crosstalk Bandwidth CS(on) CS(off) CD(off) tTRANS tOPEN tON tOFF Q XTALK(DIS) XTALK(AI) XTALK(AH) BW See Figure 11 1 In to 1 Out, See Figure 11 1 In to 4 Out, See Figure 11 Room Room Room Room Room Full Room Full Room Full Room Room Room Room Room -100 -82 -85 -66 300 MHz dB 10 300 500 175 300 30 120 8 10 20 20 40 160 20 20 300 10 300 175 pC ns pF
See Figure 5
RL= 1 kW , CL = 35 pF 50% Control to 90% Output See Figure 3 See Figure 6 RIN = RL = 75 W f = 5 MHz, See Figure 10 RIN = 10 W , RL = 10 kW f = 5 MHz, See Figure 9 RIN = 10 W , RL = 10 kW f = 5 MHz, See Figure 8 RL = 50 W , See Figure 7
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Document Number: 70071 S-52433--Rev. G, 20-Dec-04
DG884
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Specified
V+ = 15 V, V- = -3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V
A Suffix
-55 to 125_C
D Suffix
-40 to 85_C
Parameter Power Supplies
Positive Supply Current Negative Supply Current Digital GND Supply Current Logic Supply Current Functional O Operating S Supply Voltage Rangee
Symbol
Tempb
Typc
Mind
Maxd
Mind
Maxd
Unit
I+ I- IDG IL V+ to V- V- to GND V+ to GND See Operating Voltage Range ( yp ) (Typical Characteristics) page 6 All Inputs At GND or 2 V RS = 2 V
Room Full Room Full Full Full Full Full Full
1.5 -1.5 -275 200 13 -5.5 10 -3 -5 -750
3 6 -3 -5 -750 500 20 0 20 13 -5.5 10
3 6
mA
500 20 0 20
mA
V
Minimum Input Timing Requirements
Address Write Time Minimum WR Pulse Width Write Address Time Chip Select Write Time Write Chip Select Time Minimum SALVO Pulse Width SALVO Write Time Write SALVO Time Input Output Time Address Output Time Chip Select Output Time Chip Select Address Time Reset to SALVO I/O Address Input Time tAW tWP tWA tCW tWC tSP tSW tWS tIO tAO tCO tCA tRS tIA See Figure 1 Full Full Full Full Full Full Full Room Room Room Room Room Full Room 50 20 50 -10 50 25 50 -10 20 150 150 150 60 50 200 200 200 50 100 10 100 75 100 10 50 100 10 100 75 100 10 50 200 200 200 100 50 ns
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test.
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
TYPICAL CHARACTERISTICS (25_C UNLESS NOTED)
120
Adjacent Input Crosstalk
120
Matrix Disabled Crosstalk
100 X TALK(DIS)(-dB) 1 10 f - Frequency (MHz) 100 X TALK(AI) (-dB)
100
80
80
60
60
40
40
20
20 1 10 f - Frequency (MHz) 100
100
All Hostile Crosstalk
21 19 V+ - Positive Supply (V) 17 15
Operating Voltage Area
80 X TALK(AH) (-dB)
60
40
Operating Voltage Area 13 11 9
20
0 1 10 f - Frequency (MHz) 100
0
-1
-2
-3
-4
-5
-6
V- - Negative Supply (V)
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Document Number: 70071 S-52433--Rev. G, 20-Dec-04
DG884
Vishay Siliconix
TIMING DIAGRAMS
CS for Device A CS for Device B tCA Address B0 - B1 Address A0 - A3 WR tIA SALVO tCW I/O tWC Input Select Output 1 Select Output 2 Presetting Device A Don't Care
Presetting Device B
Don't Care
Output N
Select Input tAW tWA
Select Input
Input
tWP
tAW
tWA tWS tSP tSW
tAW
tWA tWS
tSW
tCW tSP
RS
Reset Occuring at Any Time Results In All Current Event Latches Being Cleared tRS
FIGURE 1. Input Timing Requirements
CS for Device A CS for Device B Address B0 - B1 Address A0 - A3
WR SALVO Output
Interrogating Device A
tC
O
Interrogating Device B
tC
Select Current Event Latch 1 Latch N
O
tC
Select Current Event Latch
A
tAO
tAO
tCA
Out N
tAO
Address Output
tAO
Address Output 1
tIO
I/O RS Reset Occuring at Any Time Results In All Current Event Latches Being Cleared
tIA
FIGURE 2. Output Timing Requirements
PARAMETER DEFINITIONS
Symbol
TAW TWA TWP TCW TWC TSP TWS TSW TIA TRS TIO TAO TCO TCA Document Number: 70071 S-52433--Rev. G, 20-Dec-04
Parameter
Address to Write Write to Address WR Pulse Chip Select to WR WR to Chip Select SALVO Pulse WR to SALVO SALVO to WR I/O to Address In RS to SALVO I/O to Output Address to Output CS to Output CS to Address In
Description
Minimum time address must be valid before WR goes high Minimum time address must remain valid after WR pulse goes high Minimum time of WR pulse width to write address into Next Event latches Minimum time chip select must be valid before a WR pulse Minimum time chip select must remain valid after WR pulse Minimum time of SALVO pulse width Minimum time from WR pulse to SALVO to load new address Minimum time from SALVO pulse to WR to load current address Minimum time I/O must be valid before address applied Minimum time RS must be valid before SALVO pulse Minimum time I/O must be valid before address output valid Minimum time address BX must be valid until address AX output valid Minimum time CS must be valid until AX output is valid Minimum time CS must be valid before address applied if I/O is high www.vishay.com
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DG884
Vishay Siliconix
TEST CIRCUITS
-3 V V- 1V IN1 GND DGND IN2 - IN8 VL 5V V+ OUT1 15 V
VO A0, A1, A2 SALVO 1 kW 35 pF
3V 0V 3V 0V 1V VO 50% 50%
DG884
90%
90%
SALVO A0, A1, A2 B0 B1 I/O CS WR A3 RS
tON
tOFF
3V
FIGURE 3. SALVO Turn On/Off Time
-3 V V- 1V IN1 GND DGND IN2 - IN8 VL 5V V+ OUT1 15 V 3V A0, A1, A2 WR 0V 3V 50% 50%
VO
DG884
1 kW
35 pF 0V VO 1V 90% 90%
WR A0, A1, A2 B0 B1 I/O CS SALVO
A3 RS
tON
tOFF
3V
FIGURE 4. WR Turn On/Off Time
-3 V V- IN1 GND DGND IN8 IN2 - IN7 VL
5V V+
15 V
1V
3V VO A0, A1, A2 VO 0V 50%
OUT1
DG884
1 kW
90% tTRANS tBBM
WR A0, A1, A2 B0 B1 I/O CS SALVO
A3 RS
3V
FIGURE 5. Transition Time and Break-Before-Make Interval
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DG884
Vishay Siliconix
TEST CIRCUITS
-3 V V- IN1 GND DGND A3 WR A0, A1, A2 B B I/O CS SALVO RS 0 1 VL 5V V+ OUT1 VO Signal Generator 50 W 15 V V- IN8 GND DGND WR A0 - A3 A3 B0 B1 I/O CS SALVO WR RS -3 V VL 5V V+ OUT1 VO 50 W 15 V
DG884
35 pF
DG884
DVO 5V Q = DV0 CL 5V
FIGURE 6. Charge Injection
FIGURE 7. -3 dB Bandwidth
Any one input to any one output--all remaining inputs connected to remaining outputs
VO Outputs RL 10 kW
Any input or output pin to adjacent input or output pin RL 10 kW Vn - 1 Vn RIN 10 W Vn + 1
10 kW RIN 10 W
Inputs
Signal Generator 75 W
V X TALK(AH) + 20 log 10 V OUT V
Signal Generator 75 W
RIN 10 W X TALK(AI) + 20 log10
Vn - 1 Vn
or 20 log10
Vn ) 1 Vn
FIGURE 8. All Hostile Crosstalk
FIGURE 9. Adjacent Input Crosstalk
All crosspoints open
Outputs RL 75 W
VO
OUT 1
OUT 2
OUT 3
Meter Inputs HP4192A Impedance Analyzer or Equivalent
IN2 IN3 IN4 IN5 IN6
DGND
OUT 4
IN 1
GND
DG884
VL RS I/O
5V
IN 8
Signal Generator 75 W
X TALK(DIS) + 20 log10
V OUT V -3 V 15 V
FIGURE 10. Matrix Disabled Crosstalk
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
FIGURE 11. On-State and Off-State Capacitances
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V-
V+
V
IN7
CS
"0" = Off-State "1" = On-State
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DG884
Vishay Siliconix
PIN DESCRIPTION
Pin
1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 41, 43 39 26 21 38 5, 7, 9, 11, 13, 15, 17, 19 2, 40, 42, 44 29 30 31, 32, 33, 34 27, 28 35 36 37 22, 23, 24, 25
Symbol
GND DGND V+ V- VL IN1 to IN8 OUT1 to OUT4 I/O CS A0, A1, A2, A3 B0, B1 WR SALVO RS DIS1 to DIS4 Analog Signal Ground Digital Ground Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage--generally 5 V 8 Analog Input Channels 4 Analog Output Channels
Description
Determines whether data is being written into the Next Event latches or read from the Current Event latches Chip Select--a logic input IN Address--logic inputs or outputs as defined by I/O pin, select one of eight IN channels OUT Address--logic inputs, select one of four OUT channels Write command that latches A0, A1, A2, A3 into the Next Event latches Master write command, that in one action, transfers all the data from Next Event latches into Current Event latches Reset--a low will clear the Current Event latches Open drain disable outputs--these outputs pull low when the corresponding OUT channel is off
DEVICE DESCRIPTION
The DG884 is the world's first monolithic wideband crosspoint array that operates from dc to >100 MHz. The DG884 offers the ability to route any one of eight input signals to any one of four OUT pins. Any input can be routed to one, two, three or four OUTs simultaneously with no risk of shorting inputs together (guaranteed by design). Each crosspoint is configured as a "T" switch in which DMOS FETs are used due to their excellent low resistance and low capacitance characteristics. Each OUT line has a series switch that minimizes capacitive loading when the OUT is off. Upon completing all crosspoint connections that are to be changed in a single device, other DG884s can be similarly preset by taking the CS pin low on the appropriate device. When all DG884s are preset, the Current Event latches are simultaneously changed by a single SALVO command applied to all devices. In this manner the crosspoint configuration of any number of devices can be simultaneously updated.
DIS Outputs Four open drain disable OUTs are provided to control external line drivers or to provide visual or electrical signaling. For example, any or all of the DIS OUTs can directly interface with a CLC410 Video Amplifier to place it into a high impedance, low-power standby mode when the corresponding OUT is not being used. (See Figure 15). The DIS outputs are low and sink to V- when corresponding OUT is open or RS is low.
Interfacing The DG884 was designed to allow complex matrices to be developed while maintaining a simple control interface. The status of the I/O pin determines whether the DG884 is being written to or read from (see Figures 1 and 2). In order to WRITE to an individual latch, CS and I/O need to be low, while RS, WR and SALVO must be high. The IN to OUT path is selected by using address A0 through A3 to define the IN line and address B0 and B1 to define the OUT line. That is, The IN defined by A0 through A3 is electrically connected to the OUT defined by B0, B1. This chosen path is loaded into the Next Event latches when WR goes low and returns high again. This operation is repeated up to three more times if other crosspoint connections need to be changed.
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Reset The reset function (RS) allows the resetting of all crosspoints to a known state (open). At power up, the reset facility may be used to guarantee that all switches are open. It should be noted that RS clears the Current Event latches, but the Next Event latches remain unchanged. This useful facility allows the user to return the matrix to its previous state (prior to reset) by simply applying the SALVO command. Alternatively, the user can reprogram the Next Event latches, and then apply the SALVO command to reconfigure the matrix to a new state.
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
DEVICE DESCRIPTION
Readback The I/O facility enables the user to write data to the Next Event latches or to read the contents of the Current Event latches. This feature permits the central controller to periodically monitor the state of the matrix. If a power loss to the controller occurs, the readback feature helps the matrix to recover rapidly. It also offers a means to perform PC board diagnostics both in production and in system operation.
8 Analog Inputs
EN CMOS Output Buffers Mux 1 8 4 / Data Buffers EN 4 /
OUT1
I/O
Mux 2 8
OUT2
RS A0 A1 A2 A3 B0 B1 CS WR Mux 3 Decoder SALVO DIS3 Open Drain Output Current Event Next Event Latch 3
Latch 3
Q0 - Q3
4 /
7 /
Decoders/ Drivers
9 /
8 T-Switches 1 Series Switch 8
OUT3
Mux 4
OUT4
One of Four Blocks of Logic/Latches Shown
FIGURE 12. Control Circuitry
APPLICATIONS
Two--Si584 Quad Unity-Gain Buffers IN1 75 W IN2 x1 DIS2 x1 DIS1 x2 OUT2 OUT3 OUT4 WR SALVO CLC410 x2 75 W OUT1
DG884
DIS3
x2
x2 IN8 x1 DIS4 RS B0 B1 A0 A1 A2 A3
Note: DIS outputs are used to power down the Si582 amplifiers.
RESET
FIGURE 13. Fully Buffered 8 X 4 Crosspoint
Document Number: 70071 S-52433--Rev. G, 20-Dec-04 www.vishay.com
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DG884
Vishay Siliconix
APPLICATIONS
+5 V +15 V
51 W
51 W 6
C2
+ C1 VL
+ C1 V+
C2 V th - Logic Threshold (V)
5 4 3
DG884
V- C1 + 51 W -3 V C2
2 1 0
C1 = 1 mF Tantalum C2 = 100 nF Ceramic
0
2
4
6
8
10
12
14
16
18
VL - Logic Supply (V)
FIGURE 14. DG884 Power Supply Decoupling
FIGURE 15. Switching Threshold Voltage vs. VL
Power Supplies and Decoupling A useful feature of the DG884 is its power supply flexibility. It can be operated from dual supplies, or a single positive supply (V- connected to 0 V) if required. Allowable operating voltage ranges are shown in Operating Voltage Range (Typical Characteristics) graph, page 6. Note that the analog signal must not go below V- by more than 0.3 V (see absolute maximum ratings). However, the addition of a V- pin has a number of advantages: 1) It allows flexibility in analog signal handling, i.e. with V- = -5 V and V+ = 15 V, up to "5-V ac signals can be accepted. The value of on-capacitance [CS(on) ] may be reduced by increasing the value of V-. It is useful to note that optimum video differential phase and gain occur when V- is -3 V. Note that V+ has no effect on CS(on) . V- eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors.
of the DG884 is adversely affected by poor decoupling of power supply pins. Also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential.
Rules: 1) 2) 3) Decoupling capacitors should be incorporated on all power supply pins (V+, V-, VL ). They should be mounted as close as possible to the device pins. Capacitors should have good high frequency characteristics--tantalum bead and/or monolithic ceramic disc types are suitable.
2)
Recommended decoupling capacitors are 1- to 10-mF tantalum bead, in parallel with 100-nF monolithic ceramic. 4) Additional high frequency protection may be provided by 51-W carbon film resistors connected in series with the power supply pins (see Figure 14).
3)
It is established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance
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The VL pin permits interface to various logic types. The device is primarily designed to be TTL or CMOS logic compatible with +5 V applied to VL. The actual logic threshold can be raised simply by increasing VL.
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
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DG884
Vishay Siliconix
APPLICATIONS
A typical switching threshold versus VL is shown in Figure 15. These devices feature an address readback facility whereby the last address written to the device may be read by the system. This allows improved status monitoring and hand shaking without additional external components. When the I/O assigns the address output condition, the AX address pins can sink or source current for logic low and high, respectively. Note that VL is the logic high output condition. This point must be respected if VL is varied for input logic threshold shifting. Note: Even though these devices are designed to be latchup resistant, VL must not exceed V+ by more than 0.3 V in operation or during power supply on/off sequencing.
Layout The PLCC package pinout is optimized so that large crosspoint arrays can be easily implemented with a minimum number of PCB layers (see Figure 16). Crosstalk is minimized and off-isolation is optimized by having ground pins located adjacent to each input and output signal pins. Optimum off-isolation and low crosstalk performance can only be achieved by the proper use of RF layout techniques: avoid sockets, use ground planes, avoid ground loops, bypass the power supplies with high frequency type capacitors (low ESR, low ESL), use striplines to maintain transmission line impedance matching.
Address Bus
Video Out Bus
Video Out Bus
Video In Bus
Address Bus
Video In Bus
Video In Bus
Video In Bus
Video Out Bus
Video Out Bus
FIGURE 16. 16 X 8 Expandable Crosspoint Matrix Using DG884
Document Number: 70071 S-52433--Rev. G, 20-Dec-04
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Legal Disclaimer Notice
Vishay
Notice
Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc., or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Vishay for any damages resulting from such improper use or sale.
Document Number: 91000 Revision: 08-Apr-05
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